Semiconductor device and interposer

ABSTRACT

A semiconductor device characterized in that connection pads for wire bonding are arranged at peripheral regions of an electrode terminal formation surface of a semiconductor chip, test pads for testing the semiconductor chip are arranged in an inside region surrounded by said peripheral regions of said electrode terminal formation surface, and a plurality of rewiring patterns extend from the peripheral regions to said inside region of said electrode terminal formation surface and the individual rewiring patterns connect the individual electrode terminals and the corresponding connection pads and test pads.

TECHNICAL FIELD

The present invention relates to a semiconductor device and aninterposer provided with test pads for testing properties of asemiconductor chip included in them.

BACKGROUND ART

Semiconductor devices, for example as disclosed in Japanese UnexaminedPatent Publication (Kokai) No. 2002-151644, include single semiconductordevices into which a plurality of semiconductor chips or a plurality ofsemiconductor devices are assembled, that is, stack semiconductordevices.

The stack semiconductor device 1 shown in FIG. 10 has a structure calleda “multi-chip package” or a “die stack”. Semiconductor chips 10 arestacked on a board 12, the semiconductor chips 10 and connectionelectrodes 13 provided on the board 12 are connected by wire bonding,one surface of the board 12 (surface on which semiconductor chips arecarried) is sealed by a sealing resin 14, and solder balls 16 areconnected to the mounting surface of the board 12.

The stack semiconductor device 2 shown in FIG. 11 has a so-called“package stack” structure. A plurality of semiconductor devices 11comprised of boards 12 on which semiconductor chips 10 are mounted byflip-chip connection are stacked. The semiconductor devices 11 areelectrically connected through solder balls 18 between the boards 12.

The stack semiconductor device 1 having the multi-chip package or diestack structure shown in FIG. 10 has the advantage of enabling aplurality of semiconductor chips 10 to be compactly housed in a singlestack semiconductor device 1.

However, there is the problem that product tests are conducted by usingthe solder balls 16 as test pads after a plurality of semiconductorchips 10 are placed on the boards 12, so if even just some of thesemiconductor chips 10 are defective, the product 1 as a whole is judgeddefective and even the good semiconductor chips 10 end up beingdiscarded.

This problem becomes more serious the greater the number of thesemiconductor chips 10 stacked. That is, if the number of thesemiconductor chips 10 stacked increases, the probability will rise ofdefective semiconductor chips 10 being included in the product 1, so thedefect rate of the product 1 will rise and good semiconductor chips 10wastefully discarded will increase.

To solve this problem, it is sufficient to test the individualsemiconductor chips 10 to judge if they are good or defective inadvance, then place them on the boards 12. However, directly testingconventional semiconductor chips 10 has been difficult due to thefollowing reasons.

That is, testing semiconductor chips 10 requires that the electrodeterminals (aluminum pads) be connected to the test apparatus, butelectrode terminals are arranged at intervals of a narrow 50 to 100 μm,so it is necessary to use a special test apparatus provided with specialsockets for connection with the electrode terminals. Due to this, theproduction costs are raised.

As opposed to this, in the case of the stack semiconductor device 2shown in FIG. 11, the semiconductor devices 11 comprised of thesemiconductor chips 10 placed on the boards 12 can be individuallytested to judge if they are good or defective in advance, then aplurality of only the good semiconductor devices 11 stacked to obtainthe product 2.

With this method, however, (1) the number of the boards 12 increases andthe production costs increase, (2) the boards 12 are joined at the boardperipheries at the outside from the regions for carrying thesemiconductor chips 10, so the planar dimensions of the semiconductordevices 11 and in the end the planar dimensions of the stacksemiconductor device 2 cannot be reduced, and (3) since a plurality ofnot only semiconductor chips 10 and boards 12 are stacked, the stacksemiconductor device 2 as a whole increases in thickness.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a semiconductor deviceenabling properties of semiconductor chips assembled in it to be easilytested without requiring any special test apparatus, carrying only goodsemiconductor chips and thereby improving the product yield, and able tobe produced by existing facilities to keep production costs to aminimum.

Another object of the present invention is to provide an interposerenabling properties of semiconductor chips assembled in it to be easilytested without requiring any special test apparatus, carrying only goodsemiconductor chips and thereby improving the product yield, andenabling production of semiconductor devices by existing facilities tokeep production costs to a minimum.

To achieve the above objects, according to a first aspect of theinvention, there is provided a semiconductor device wherein

connection pads for wire bonding are arranged at peripheral regions ofan electrode terminal formation surface of a semiconductor chip,

test pads for testing the semiconductor chip are arranged in an insideregion surrounded by said peripheral regions of said electrode terminalformation surface, and

a plurality of rewiring patterns extend from the peripheral regions tosaid inside region of said electrode terminal formation surface andindividual rewiring patterns connect the individual electrode terminalsand the corresponding connection pads and test pads.

Typically, said test pads are arranged in an array on said insideregion.

Typically, said electrode terminals are exposed from openings of aprotective insulation layer covering said electrode terminal formationsurface, said rewiring patterns extend on said protective insulationlayer and are connected to said electrode terminals via said openings,said rewiring patterns and said protective insulation layer are furthercovered by an insulation layer, and said connection pads and said testpads connected to said rewiring patterns are exposed from openings ofsaid insulation layer.

In the first aspect of the invention, there is further provided asemiconductor device comprised of one or a stack of a plurality of theabove semiconductor device as an element semiconductor device or a stackof one or more of each of said element semiconductor device and asemiconductor chip carried on a wiring board, said semiconductor devicecharacterized in that

connection pads of each said element semiconductor device and connectionelectrodes of said wiring board are connected by wire bonding, and

each said element semiconductor device and/or each said semiconductorchip is sealed by resin on said wiring board.

Further, to achieve the above objects, according to a second aspect ofthe invention, there is provided an interposer characterized in that

connection pads for wire bonding to be connected to a wiring board arearranged at peripheral regions of one surface of the interposer forcarrying a semiconductor chip,

test pads for testing the semiconductor chip are arranged in an insideregion surrounded by said peripheral regions of said one surface or theother surface, and

a plurality of rewiring patterns extend from said peripheral regions tosaid inside region and the individual rewiring patterns connect thecorresponding connection pads and test pads.

Typically, said test pads are arranged in an array in said insideregion.

In the second aspect of the invention, further, there is provided asemiconductor device comprised of a semiconductor module, comprised ofsaid interposer on the surface of which, opposite to the surface wheresaid test pads are arranged, one or a plurality of said semiconductorchips are stacked, carried on a wiring board,

said semiconductor device characterized in that

connection pads of said interposer and connection electrodes of saidwiring board are connected by wire bonding, and

said semiconductor module is sealed by resin on said wiring board.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a plan view of an electrode terminal formation surface of asemiconductor device according to a first aspect of the invention.

FIG. 2 is a cross-sectional view of the positional relationship ofconnection pads, test pads, and electrode terminals of a semiconductordevice according to the first aspect of the invention.

FIGS. 3A to 3H are cross-sectional views of steps of production of asemiconductor device according to the first aspect of the invention.

FIG. 4 is a cross-sectional view of an example of the configuration of asemiconductor device according to the first aspect of the invention.

FIG. 5 is a cross-sectional view of another example of the configurationof a semiconductor device according to the first aspect of theinvention.

FIG. 6 is a cross-sectional view of still another example of theconfiguration of a semiconductor device according to the first aspect ofthe invention.

FIG. 7 is a cross-sectional view of an example of the configuration of asemiconductor device using an interposer according to a second aspect ofthe invention.

FIG. 8 is a cross-sectional view of another example of the configurationof a semiconductor device using an interposer according to the secondaspect of the invention.

FIG. 9 is a cross-sectional view of still another example of theconfiguration of a semiconductor device using an interposer according tothe second aspect of the invention.

FIG. 10 is a cross-sectional view of an example of the configuration ofa conventional semiconductor device.

FIG. 11 is a cross-sectional view of another example of theconfiguration of a conventional semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

Below, preferred embodiments of the present invention will be explainedwith reference to the attached drawings.

EXAMPLE 1

FIG. 1 is a plan view of an example of a semiconductor device accordingto a first aspect of the invention and shows an example of theconfiguration of the characterizing electrode terminal formationsurface. The illustrated semiconductor device 20 is obtained by formingwiring patterns all together on an electrode terminal formation surfaceof a semiconductor wafer, then dicing the semiconductor wafer intoindividual semiconductor chips.

The semiconductor device 20 is provided with connection pads 22 insingle rows along peripheral regions of an electrode terminal formationsurface of a semiconductor chip 10 and is provided with test pads 24 inan array of a plurality of rows in an inside region surrounded by theperipheral regions.

When mounting the semiconductor device 20 on a mounting board etc., theconnection pads 22 of the semiconductor device 20 and the connectionterminals of the mounting board are connected by wire bonding. By theconnection pads 22 being provided in single rows along the peripheralregions of the semiconductor device 20 (=peripheral regions of thesemiconductor chip 10), the above wire bonding becomes easy. Theindividual connection pads 22, as explained later, connect with theindividual electrode terminals of the semiconductor chip 10 throughrewiring patterns.

The test pads 24 are used for connection with a test apparatus whentesting the properties of the semiconductor chip 10. The individual testpads 24, as explained later, connect with the individual electrodeterminals of the semiconductor chip 10 through rewiring patterns thesame as above.

To make the semiconductor chip 10 and the semiconductor device 20 assmall as possible, the connection pads 22 are made the smallest planardimensions enabling wire bonding and arranged at a high density insingle rows. On the other hand, a large area region is left unused atthe inside from the peripheral regions where the connection pads 22 arearranged. In the present invention, this large area inside region iseffectively utilized to enable test pads 24 to be arranged in largeplanar dimensions and large intervals. Here, the connection pads 22 inpractice have to be arranged in one row or two rows in order to ensureease of wire bonding. As opposed to this, the test pads 24, which haveno relation to wire bonding, can be arranged in an array of a pluralityof rows, so can make full use of the large area of the inside region.This is also extremely advantageous in enlarging the planar dimensionsand intervals of the test pads 24.

In this way, by arranging the test pads 24 in large planar dimensions atwide intervals, it is possible to test the properties of thesemiconductor chip 10 without requiring a specialized test apparatusprovided with sockets etc. having special probes.

FIG. 2 is a cross-sectional view of the semiconductor device 20 shown inFIG. 1 and shows the positional relationship of the connection pads 22,test pads 24, and electrode terminals 26. The electrode terminals 26 areformed as aluminum pads on the electrode terminal formation surface 10Sof the semiconductor chip 10. The electrode terminal formation surface10S of the semiconductor chip 10 is covered over its entirety other thanthe electrode terminals 26 with a protective insulation layer 28. Thesurface of the protective insulation layer 28 is formed with rewiringpatterns 30 and is covered over that with an insulation layer 32. Theconnection pads 22 and the test pads 24 are directly formed atpredetermined locations on the rewiring patterns 30 and are exposedthrough the through holes of the insulation layer 32.

That is, the rewiring patterns 30 extend from the electrode terminals 26over the protective insulation layer 28 to the peripheral regions andinside region of the semiconductor chip 10. At the peripheral regions,ends 30 a are connected to the connection pads 22, while at the insideregion, ends 30 b are connected to the test pads 24.

By leading out ends 30 a of the wiring patterns 30 from the electrodeterminals 26 up to the peripheral regions and connecting them to theconnection pads 22, wire bonding with the connection pads 22 becomeseasier and simultaneously the inside region for arrangement of the testpads 24 is secured wider.

In this example, the test pads 24 are arranged in an array, so therewiring patterns 30 for connecting the connection pads 22 and the testpads have to be arranged so as not to interfere with each other. Ofcourse, the arrangement of the test pads 24 does not have to be limitedto the array shown in the present example. The pads may be arrangedfreely.

Note that in the present example, the electrode terminals 26 are shownarranged in single rows at the regions close to the periphery of theelectrode terminal formation surface 10S, but the arrangement of theelectrode terminals in the semiconductor device of the present inventiondoes not have to be limited to this. For example, even if a plurality ofelectrode terminals are arranged in a region close to the center of theelectrode terminal formation surface, by suitably designing the rewiringpatterns 30, it is possible to apply the configuration of the presentinvention of arranging the connection pads 22 at the peripheral regionsof the electrode terminal formation surface and arranging the test pads24 at the inside region.

FIGS. 3A to 3H are cross-sectional views of an example of the productionsteps of a semiconductor device according to the present invention.

FIG. 3A is a cross-sectional view of part of a semiconductor wafer 10 a.An electrode terminal formation surface 10S is covered by a protectiveinsulation layer 28 at parts other than the electrode terminals 26comprised of aluminum pads. The protective insulation layer 28 may be apassivation film covering the electrode terminal formation surface 10Sof the semiconductor wafer 10 a used as it is or the passivation filmfurther covered by a polyimide or other resin film for strengthening itsprotective action and insulation action.

Next, as shown in FIG. 3B, as pretreatment for forming the rewiringpatterns 30 (FIG. 2) for connection to the electrode terminals 26 byplating, sputtering etc. is used to form over the entire top surface ofthe wafer 10 a (top surface of protective insulation layer 28, wallsurfaces of openings 26 a through which electrode terminals 26 areexposed, and top surfaces of electrode terminals 26) a plating powerlayer 27. The plating power layer 27 is for example comprised of achromium layer, copper layer, etc.

As shown in FIG. 3C, photolithography and resin curing processing areperformed to form photoresist patterns 29 as a plating mask on locationsother than the locations scheduled for formation of the rewiringpatterns 30 on the plating power layer 27.

As shown in FIG. 3D, the plating power layer 27 is used forelectroplating copper so as to form an electroplated copper layer 31 onthe plating power layer 27 at locations not covered by the mask 29. Theobtained electroplated copper layer 31 forms a conductive layercontinuing from the surfaces of the electrode terminals 26 exposed atthe openings 26 a through the wall surfaces of the openings 26 a to theprotective insulation layer 28.

As shown in FIG. 3E, the photoresist patterns 29 used as the platingmask are removed to expose the underlying plating power layer 27, thenthe metal forming the power layer is etched lightly using an etchingsolution so as to selectively remove only the exposed plating powerlayer 27. Due to this, rewiring patterns 30 are formed at onlypredetermined locations.

The plating power layer 27 need only be a temporary conductive layerable to supply plating current at the time of start of plating, so isformed extremely thin by sputtering etc. as explained above and so issimply removed by light etching. As opposed to this, the copperelectroplated layer 31 must form permanent rewiring patterns 30, so isformed to a sufficient thickness adding the margin for removal by theabove light etching. Therefore, it is possible to selectively removeonly the thin plating power layer 27.

Due to this, rewiring patterns 30 connecting the electrode terminals 26and extending on the protective insulation layer 28 are obtained.

As shown in FIG. 3F, the entire surface of the semiconductor wafer 10 awhere the rewiring patterns 30 are formed is covered by a photosensitivepolyimide or other photosensitive resin film 32′.

As shown in FIG. 3G, the coating layer 32′ of the photosensitive resinfilm is exposed and developed, whereby openings 22 a are formed atscheduled locations for formation of the connection pads and openings 24a are formed at scheduled locations for formation of the test pads.

As shown in FIG. 3H, by electroplating nickel and electroplating goldusing the rewiring patterns 30 as plating power layers, connection pads22 and test pads 24 are formed in the openings 22 a and openings 24 a.

Due to this, the structure of the present invention where the pluralityof rewiring patterns 30 extending from the peripheral regions to theinside region of the electrode terminal formation surface 10S connectthe individual electrode terminals 26 and the corresponding connectionpads 22 and test pads 24 is obtained.

The above production steps do not require any special test apparatus orother specialized facilities from the conventional method used forformation of rewiring patterns on a semiconductor wafer and can beeasily performed by existing production facilities.

The semiconductor device 20 shown in FIG. 1 is obtained by formingconnection pads 22 and test pads all together on an effective surface ofa semiconductor wafer 10 a by the above production steps, then dicingthe wafer into individual semiconductor chips 10. The thus obtainedsemiconductor device 20 is a so-called “chip size package”.

The semiconductor device 20 is provided with test pads 24, so it ispossible to finish the testing of properties in advance, then mount onlygood pieces in the products. The test pads 24 may be used to therequired inspections of the high frequency characteristics etc.

Further, the semiconductor device 20 is provided with connection pads 22for wire bonding, so can be mounted on a wiring board by wire bonding inexactly the same way as a conventional semiconductor device.

For example, the semiconductor device 25X shown in FIG. 4 is an examplecomprised of the semiconductor device (chip size package) 20 of FIG. 1mounted on a wiring board 40. The exact same procedure is followed aswith a conventional chip size package to bond the device on the mountingsurface of the wiring board 40, then the connection pads 22 of thesemiconductor device 20 are connected to the connection electrodes 42 ofthe wiring board 40 by wire bonding, then a sealing resin 36 is used forsealing. In the figure, 34 is a bonding wire, while 44 is a solder ballor other external connection terminal.

The semiconductor device 25Y shown in FIG. 5 is an example comprised ofa wiring board 40 on which conventional semiconductor chips 20 a and 20b and a semiconductor device 20 of the present invention are stacked. Inthis example, the conventional semiconductor chips 20 a and 20 b arearranged at the bottommost level (side close to wiring board 40) and thetopmost level and the semiconductor device 20 of the present inventionis arranged in the center level sandwiched between the two. Thesemiconductor device 20 of the present invention is formed to the chipsize, so can be stacked on the wiring board 40 in exactly the same wayas the conventional semiconductor chips 20 a and 20 b. Further, thesemiconductor chips 20 a and 20 b and the semiconductor device 20 can beconnected with the connection electrodes 42 of the wiring board 40 bywire bonding by exactly the same method as a conventional semiconductordevice using existing facilities.

As shown in FIG. 4 and FIG. 5, since the semiconductor device 20 of thepresent invention can be tested in advance for properties to judgequality, then only good quality piece mounted, it is possible to greatlyimprove the yield at the stage of producing the completed products 25Xand 25Y of the semiconductor device.

In the example shown in FIG. 5, only the semiconductor chip at thecenter among the stacked semiconductor chips was formed as the testablesemiconductor device 20 of the present invention. All of thesemiconductor chips mounted may also be made semiconductor devices 20provided with test pads 24 according to the present invention, butproviding only the semiconductor chip requiring testing of properties inadvance with test pads to make it a semiconductor device 20 of thepresent invention is effective from the viewpoint of the productioncosts.

Further, the semiconductor device 20 of the present invention having thetest pads 24 can be made the chip size in the same way as an ordinarysemiconductor chip not having test pads 24, so products mounting thesestacked together can be made compact in the same way as the past.

The semiconductor device 20 of the present invention can be used invarious forms. For example, the semiconductor device 25Z shown in FIG. 6is an example of a wiring board 40 mounted in advance with asemiconductor chip 20 e by flip-chip connection and on which asemiconductor module 25M including the semiconductor device 20 of thepresent invention is mounted.

The semiconductor module 25M is formed by stacking ordinarysemiconductor chips 20 c and 20 d not provided with test pads on theback surface of a semiconductor device 20 of the present inventionprovided with test pads 24 (surface at opposite side to electrodeterminal formation surface), connecting the semiconductor chips 20 c and20 d and the electrodes 21 provided on the back surface of thesemiconductor device 20 by wire bonding, then sealing by a sealing resin38.

The semiconductor module 25M is mounted on the wiring board 40 bybonding the sealing resin side surface of the semiconductor module 25Mon the top surface of the semiconductor chip 20 e bonded to the wiringboard 40. The connection pads 22 of the semiconductor device 20 of thesemiconductor module 25 mounted and the connection electrodes 42 of thewiring board 40 are connected by wire bonding and sealed by a sealingresin 36, whereby the semiconductor device 25Z is completed.

As explained above, the semiconductor device 20 of the present inventioncan not only be used alone, but can also be used as a combination of aplurality of semiconductor devices 20 or as a combination with ordinarysemiconductor chips. The semiconductor device 20 of the presentinvention is formed to the chip size, so is easy to use in combinationwith ordinary semiconductor chips.

The semiconductor device of the present invention can be obtained byconducting tests in advance and only assembling good pieces into theproduct, so the product yield is improved and as a result the productioncosts are reduced. The test pads and connection pads can be easilyformed on the electrode terminal formation surface of the semiconductorchip at a low cost by the conventional step of forming rewiring patternson the semiconductor wafer, so the yield can be improved and thereforethe costs greatly improved and the overall production costs reduced. Inparticular, when mounting a high performance semiconductor chip, sincethe required properties can be tested for in advance before mounting,waste can be eliminated and the production costs can be effectivelyreduced.

EXAMPLE 2

FIG. 7 is a cross-sectional view of a semiconductor device 55X using aninterposer according to a second aspect of the invention.

The semiconductor device 55X is comprised of an ordinary wiring board 41mounting in advance an ordinary (no test pad) semiconductor chip 20 e bywire bonding connection and a semiconductor module 55M including aninterposer 50 of the present invention carried on it.

The interposer 50 of the present invention is provided with connectionpads 52 for wire bonding and test pads 54 for testing the properties ofsemiconductor chips on the same surface. The test pads 54 are connectedwith the individually corresponding connection pads 52 by rewiringpatterns (not shown). The interposer 50 is for example an ordinaryprinted wiring board. The connection pads 52 and the test pads 54 arepreferably metal plated on their surfaces.

The semiconductor module 55M is formed by stacking ordinarysemiconductor chips 50 c and 50 d on the back surface of the interposer50 (surface at opposite side to surface where connection pads 52 andtest pads 54 are arranged), connecting the semiconductor chips 50 c and50 d and the electrodes 51 provided on the back surface of theinterposer 50 by wire bonding, then sealing by a sealing resin 56. Theelectrodes 51 of the interposer 50 are connected to individuallycorresponding connection pads 52 and are connected to test pads 54through the connection pads 52. Due to this, it is possible to easilytest the properties of the semiconductor chips 50 c and 50 d through thetest pads 54 of the interposer 50.

The semiconductor module 55M is mounted on the wiring board 41 bybonding the sealing resin side surface of the semiconductor module 55Mon the top surface of the semiconductor chip 20 e bonded to the wiringboard 41. The connection pads 52 of the interposer 50 of the presentinvention of the semiconductor module 55 mounted and the connectionelectrodes 42 of the wiring board 41 are connected by wire bonding andsealed by a sealing resin 36, whereby the semiconductor device 55X iscompleted.

Among the semiconductor chips 50 c, 50 d, and 20 e forming thesemiconductor device 55X, the semiconductor chips 50 c and 50 d havealready been judged good in quality by the test of properties in thestate of the semiconductor module 55M. Since it is possible to usesemiconductor modules 55M mounting only good quality chips, only thesemiconductor chip 20 e may include defects. Therefore, the yield isimproved compared with conventional semiconductor devices of the sametype.

Further, the semiconductor chips are connected by wire bonding. Thepackage does not become remarkably larger like with the case ofconnection using solder balls.

Note that as the normal semiconductor chips, two, 50 c and 50 d, wereassembled into the semiconductor module, but of course the number ofsemiconductor chips assembled does not have to be limited to this. Oneor three or more are also possible.

The semiconductor device 55Y shown in FIG. 8 has a basic configurationthe same as the semiconductor device 55X of FIG. 7, but differs in thepoint that the semiconductor chips 50 c and 20 e are connected to theinterposer 50 of the present invention and the wiring board 41 byflip-chip connection. As the flip-chip connection method, a knowntechnique can be used. For example, the method of flip-chip connectionby joining stud bumps 58 formed in advance on the semiconductor chips 50c and 20 e by solder (not shown) formed in advance on the wiring board41 may be used. By applying flip-chip connection to the semiconductorchips 50 c and 20 e, the size can be further reduced compared with theexample of FIG. 7.

In the examples of FIG. 7 and FIG. 8, connection pads 52 and test pads54 were provided on the same surface of the interposer 50 of the presentinvention, but there is no need to limit the surface where theconnection pads and test pads are arranged in the present invention tothe same surface.

For example, in the semiconductor device 55Z shown in FIG. 9, theinterposer 60 of the present invention is provided on one surface (topsurface in the figure) with connection pads 52 and semiconductor chipconnection terminals (not shown) and is provided on the other surface(bottom surface in the figure) with test pads 54. The test pads 54 areconnected with the corresponding connection pads 52 by rewiring patterns(not shown). The semiconductor chip 50 c is connected by flip-chipconnection with the semiconductor chip connection terminals on said onesurface (top surface) of the interposer 60. As a result, a semiconductormodule comprised of an interposer 60 and a semiconductor chip 50 c isobtained. Semiconductor chips 50 c are tested for properties and judgedfor quality through the test pads 54 of the interposer 60. Onlysemiconductor modules including good semiconductor chips 50 c are usedfor the next step.

Next, in the same way as the example explained in FIG. 7, the above goodsemiconductor module (60+50 c) is mounted on an ordinary wiring board 41mounting an ordinary (no test pad) semiconductor chip 20 e by flip-chipconnection. After this, the interposer 60 of the present invention andthe wiring board 41 are connected by bonding wires 34 then sealed by asealing resin 36, whereby the semiconductor device 55Z is completed.

In this example, a single resin sealing operation is enough, so comparedwith the case of FIG. 7 where the resin sealing operation is performedtwice, the cost can be reduced by that amount. At the same time, sincethere is no need to add extract thickness for the sealing resin, thesemiconductor device 55Z as a whole can be made thinner.

INDUSTRIAL APPLICABILITY

The semiconductor device and interposer of the present invention areprovided with test pads for testing the properties of semiconductorchips, so it is possible to judge quality in advance by tests and mountonly good pieces, so it is possible to prevent product defects due tomounting of defective semiconductor chips and thereby possible toimprove the product yield.

Further, the semiconductor device of the present invention is formed ina chip size, so it is possible to mount it in the same way as anordinary semiconductor chip and obtain a compact semiconductor device.

Further, the semiconductor device of the present invention can be easilystacked in a plurality of units or stacked with ordinary semiconductorchips, so it is possible to provide various types of semiconductordevices.

1. A semiconductor device, comprising: wire bonding connection pads atperipheral regions, surrounding an inside region, of an electrodeterminal formation surface of a semiconductor chip; test pads to testthe semiconductor chip, arranged in the inside region; and a pluralityof rewiring patterns, extending from respective peripheral regions tothe inside region of said electrode terminal formation surface,individual ones of the plurality of rewiring patterns connectingrespective, individual electrode terminals and corresponding connectionpads and test pads.
 2. The semiconductor device as set forth in claim 1,wherein one or more of said semiconductor devices and a semiconductorchip are carried on a wiring board, connection pads of each saidsemiconductor device and connection electrodes of said wiring board areconnected by wire bonding, and each said semiconductor device and/oreach said semiconductor chip is sealed by resin on said wiring board. 3.A semiconductor device as set forth in claim 1, wherein the electrodeterminals are exposed through openings of a protective insulation layercovering said electrode terminal formation surface, the rewiringpatterns extend on said protective insulation layer and are connected tosaid electrode terminals via said openings, said rewiring patterns andsaid protective insulation layer are further covered by an insulationlayer, and said connection pads and said test pads, connected to saidrewiring patterns, are exposed through openings in said insulationlayer.
 4. The semiconductor device as set forth in claim 3, wherein oneor more of said semiconductor devices and a semiconductor chip arecarried on a wiring board, connection pads of each said semiconductordevice and connection electrodes of said wiring board are connected bywire bonding, and each said semiconductor device and/or each saidsemiconductor chip is sealed by resin on said wiring board.
 5. Asemiconductor device as set forth in claim 1, wherein: the test pads arearranged in an array on the inside region.
 6. A semiconductor device asset forth in claim 5, characterized in that said electrode terminals areexposed through openings in a protective insulation layer covering saidelectrode terminal formation surface, said rewiring patterns extend onsaid protective insulation layer and are connected to said electrodeterminals via said openings, said rewiring patterns and said protectiveinsulation layer are further covered by an insulation layer, and saidconnection pads and said test pads connected to said rewiring patternsare exposed through openings in said insulation layer.
 7. Thesemiconductor device as set forth in claim 5, wherein one or more ofsaid semiconductor devices and a semiconductor chip are carried on awiring board, connection pads of each said semiconductor device andconnection electrodes of said wiring board are connected by wirebonding, and each said semiconductor device and/or each saidsemiconductor chip is sealed by resin on said wiring board.